Nxp semiconductors

Overview

We are looking for a Principal HW DFT Engineer who will architect, implement, and validate in-vehicle networking devices as part of NXP’s Automotive grade products. You will be responsible for advanced test strategies and implementation, verification and validation of pre/post tapeout of DFT features, overall test coverage improvements, and work closely with RTL and physical team on DFT timing constraints and closures.

About Nxp semiconductors

NXP Semiconductors N.V. enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.

Requirements & Eligibility

• Education: B.S./M.S. Electrical/Computer Engineering (or similar degrees)
• Experience: Typically requires 10+ years of industry experience in SoC DFT implementation, verification, static timing closure, test coverage analysis and improvement, and silicon bring-up on ATE
• Proficiency with industry-standard EDA tools from Mentor Graphics/Siemens (Tessent), Cadence, or Synopsys
• Strong command of Verilog or SystemVerilog for modifying RTL to insert test logic and writing test wrappers
• Expertise in Tcl, Python, or Perl to automate test insertion flows, run simulations, and parse coverage reports

Key Responsibilities

• Define and implement advanced DFT strategies, including Scan Architecture, JTAG, Memory BIST (MBIST), and Logic BIST (LBIST)
• Lead the integration of digital subsystems, perform scan insertion, and generate ATPG (Automatic Test Pattern Generation) patterns while ensuring high fault coverage
• Drive post-silicon validation and debug activities to root cause failures and improve manufacturing test efficiency
• Coordinate with physical design and test engineering teams to ensure timing closure and that test patterns are operational immediately upon silicon arrival