Role Overview
Apply advanced formal methods to rigorously verify interconnect fabrics, protocol bridges, and link-layer logic. Drive end-to-end formal verification processes, including property specification and proof convergence across multiple protocol domains.
About Intel
Intel is seeking a Formal Verification Engineer for the Silicon Chassis team. The Central Engineering Group (CEG) focuses on enabling technology innovation across Intel by delivering robust engineering solutions and methodologies.
Key Responsibilities
- Develop and execute formal verification test plans, including defining scope, strategies, and methodologies
- Create abstraction models to facilitate convergence on complex designs and apply abstraction techniques for formal analysis
- Generate and validate proofs to verify designs, troubleshoot failing tests, and implement corrective measures
- Collaborate across architecture, RTL design, and physical implementation teams to improve verification accuracy for advanced features
- Maintain and enhance formal verification tools, methodologies, and infrastructure for optimized workflows
- Simplify and model design verification challenges using architecture-level modeling techniques
- Utilize formal verification tools to resolve Binary Decision Diagrams (BDD) complexities and optimize data paths
- Document verification plans, track progress, and lead technical reviews with cross-functional teams
Requirements & Eligibility
- Bachelor's degree in Electrical Engineering, Computer Science, or a related field, with 4+ years of professional experience in formal verification OR Master's degree in a relevant field, with 3+ years of experience OR PhD with no prior professional e
- Proficiency in formal verification tools and methodologies, including model checking and equivalence checking
- Strong knowledge of System Verilog, Verilog, and fundamentals of logic/microarchitecture
- Experience with abstraction modeling, simulation techniques, and convergence strategies
- Familiarity with Binary Decision Diagrams (BDD) and Data Flow Graphs (DFG)
Required Skills & Tech
System VerilogVerilogFormal VerificationModel CheckingEquivalence CheckingBinary Decision DiagramsData Flow Graphs