Tenstorrent

Overview

Tenstorrent is looking for a Front End Design Verification Engineer to help verify the fetch unit for our next generation of high-performance RISC-V CPU cores. You will work on the logic responsible for keeping the processor fed with the right instructions at the right time—from instruction fetch and prediction through decode and dispatch.

About Tenstorrent

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have develope

Requirements & Eligibility

• 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs.
• Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development.
• Solid understanding of CPU architecture, with familiarity in areas such as pipelines, instruction fetch/decode, branch prediction, speculative execution, or out-of-order execution.
• Experience debugging RTL and simulation failures using waveforms and standard simulation/debug tools.
• Strong programming skills in C/C++ and/or Python, with the ability to collaborate effectively across architecture, RTL, DV, and software teams.

Key Responsibilities

• Verify the fetch unit for our next generation of high-performance RISC-V CPU cores.
• Work on the logic responsible for keeping the processor fed with the right instructions at the right time—from instruction fetch and prediction through decode and dispatch.
• Partner closely with CPU architects and RTL designers to develop verification strategies, create sophisticated tests, debug complex failures, and ensure the front end behaves correctly across a wide range of workloads and corner cases.

Interview Process